This is the implementation of circuit simplication simplification. By means of unused gate sweeping, trivial optimization, simplification by structural hash, and previous simulation, I try to preliminarily simplify the circuits in an efficient manner. After that, I also apply Equivalence gate merging to the circuits using Boolean Satisfiability (SAT) solver. I collected functionally equivalent candidates (FEC) by circuit simulation. Each simulation can split different FEC into groups. However, the number of simulation times was crucial for the performance. Therefore, I dynamically adjusted the stopping criteria of the simulation according to the splitting times of FEC.